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? semiconductor components industries, llc, 2008 january, 2008 - rev. 3 1 publication order number: ncp3102/d ncp3102 wide input voltage synchronous buck converter the ncp3102 is a high efficiency, 10 a dc-dc buck converter designed to operate from a 5 v to 13.2 v supply. the device is capable of producing an output voltage as low as 0.8 v. the ncp3102 can continuously output 10 a through mosfet switches driven by an internally set 275 khz oscillator. the 40-pin device provides an optimal level of integration to reduce size and cost of the power supply. the ncp3102 also incorporates an externally compensated transconductance error amplifier and a capacitor programmable soft-start function. protection features include programmable short circuit protection and under voltage lockout (uvlo). the ncp3102 is available in a 40-pin qfn package. features ? input voltage range from 4.5 v to 13.2 v ? 275 khz internal oscillator ? greater than 90% maximum efficiency ? boost pin operates to 25 v ? voltage mode pwm control ? 0.8 v 1% internal reference voltage ? adjustable output voltage by resistor divider ? capacitor programmable soft-start ? 80% maximum duty cycle ? input undervoltage lockout ? resistor programmable current limit ? this is a pb-free device applications ? servers/networking ? dsp and fpga power supply ? dc-dc regulator modules figure 1. typical application diagram ncp3102 vout vin tgout tgin pwrphs cphs pwrvcc bst vcc comp/dis fb agnd bg pwrgnd gnd gnd 100 95 90 85 80 75 70 65 60 55 50 01234 5678 910 output current (a) efficiency (%) figure 2. efficiency v in = 5.0 v v in = 12 v qfn40 case 485ak marking diagram a = assembly location wl = wafer lot yy = year ww = work week g = pb-free package http://onsemi.com ncp3102 awlyywwg see detailed ordering and shipping information in the package dimensions section on page 16 of this data sheet. ordering information pin connections (top view) 40 1
ncp3102 http://onsemi.com 2 figure 3. detailed block diagram - + - + - + - + - + - + 13 24 21 25 26-34 vcc bst tgout tgin pwrvcc 16 17 fb comp dis 1-4 36-40 22 pwrphs cphs 14,15,19,20,23 35 5-12 agnd bg pwrgnd r s q pwm out latch osc osc ramp clock por uvlo 0.8v 0.4v 50mv-550mv vocth fault vcc fault fault 2v vocth set 2v 10 a v ref cphs fault pin function description pin no symbol description 1-4 , 36-40 pwrphs power phase node. drain of the low side power mosfet and source of the high side mosfet. 5-12 pwrgnd power ground. source of the low side power mosfet. connected with large copper area. high current return for the low side mosfet. 13 v cc supply for the internal driver. decouple with a 0.1 f - 1 f capacitor to agnd as close to the ic as possible. 14,15,19,20,23 agnd internal driver ground. reference ground for fb, comp and other driver circuits. 16 fb the input pin to the error amplifier.(inverted input error amplifier) connect this pin to the output resistor divider (if used) or directly to the output voltage near the load connection. 17 comp/dis compensation or disable pin. (output error amplifier) use this pin to compensate the voltage control feedback loop. the compensation capacitor also acts as a soft-start capacitor. pulling the pin below 400 mv will disable the controller. 18 nc no connect. this pin can be connected to agnd or not connected. 21 tgout output high side mosfet driver. 22 cphs the controller phase sensing. 24 bst supply rail for the floating top gate driver. 25 tgin gate high side mosfet 26-34 pwrvcc input supply pins for the high side mosfet. (drain) 35 bg the current limit set pin.
ncp3102 http://onsemi.com 3 absolute maximum ratings pin name symbol v max v min control circuitry input voltage v cc 15 v -0.3 v main supply voltage input pwrvcc 30v -0.3 v bootstrap supply voltage input bst 30 v wrt/gnd 15 v wrt/phase -0.3 v phase node pwrphs 25 v -0.7 v -5 v for < 50 nsec phase node (bootstrap supply return) cphs 25 v -0.7 v -5 v for < 50 nsec current limit set bg 15v -0.3v -2.0 v for < 200 nsec feedback fb 5.5 v -0.3 v comp/disable comp/dis 5.5 v -0.3 v maximum ratings pin name symbol value unit thermal resistance junction-to-ambient (note 2) r ja 35 c/w operating junction temperature range t j -40 to 150 c storage ambient temperature t stg -55 to 150 c thermal characteristics 6x6 qfn plastic package maximum power dissipation @ t a = 25 c p d 3000 mw lead temperature soldering (10 sec): reflow (smd styles only) pb_free (note 1) 260 peak c moisture sensitivity level msl 3 - stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. note: these devices have limited built-in esd protection. the devices should be shorted together or the device placed in conduct ive foam during storage or handling to prevent electrostatic damage to the device. 1. 60-180 seconds minimum above 237 c 2. based on 110*100 mm double layer pcb with 35 m thick copper plating.
ncp3102 http://onsemi.com 4 electrical characteristics (0 c < t j < 70 c for ncp3102, -40 c < t j < 125 c for ncp3102b, 4.5 v < v cc < 13.2 v, bst = v cc * 2) characteristic conditions min typ max unit input voltage range - 4.5 13.2 v boost voltage range - 4.5 26.5 v quiescent supply current v fb = 1.0 v , no switching, v cc = 13.2 v 2.3 3.5 ma quiescent supply current v fb = 1.0 v , no switching, v cc = 5 v 1.8 ma v cc supply current v fb = 0.5 v , switching, v cc = 13.2 v 10.3 25 ma v cc supply current v fb = 0.5 v , switching, v cc = 5 v 5.6 12.5 ma boost quiescent current v fb = 1.0 v , no switching, v bst = 25 v 600 a uvlo threshold v cc rising edge 3.6 4 v uvlo hysteresis 0.4 v v fb feedback voltage t j = 0 c to 70 c 0.792 0.8 0.808 v v fb feedback voltage t j = -40 c to 125 c 0.788 0.8 0.812 v oscillator frequency t j = 0 c to 70 c 250 275 300 khz oscillator frequency t j = -40 c to 125 c 233 275 317 khz minimum duty cycle 4 % maximum duty cycle 70 75 80 % blanking time 50 ns transconductance 2 3 5 ms open loop dc gain guaranteed by design 55 70 db output source current v fb - 100 mv 80 120 a output sink current v fb + 100 mv 80 120 a input bias current 0.1 1 a unity gain bandwidth guaranteed by design 4 mhz soft-start source current v fb = 0.8 v 7 10 17 a transient response* undershot v out recovery time 71 180 mv s overcurrent protection oc threshold r bg = 5 k 50 mv fixed oc threshold - -375 - mv ocset current source sourced from bg pin before soft-start 10 a oc switch-over threshold 700 mv output power mosfets r ds(on) low-side v = 12.0 v i d = 10 a 8 m r ds(on) high-side v = 12.0 v i d = 10 a 8 m *transient response with 2.5 a/ s load step 50% - 100% defined at output parts: c out = 2x100 uf mlcc + 1 mf os-con.
ncp3102 http://onsemi.com 5 typical operating characteristics t j , junction temperature ( c) i cc , supply current switching (ma) t j , junction temperature ( c) f sw , frequency (khz) figure 4. oscillator frequency (f sw ) vs. temperature figure 5. i cc vs. temperature 801.5 -25 0 25 50 75 100 125 t j , junction temperature ( c) v ref , reference voltage (mv) t j , junction temperature ( c) uvlo rising/falling (v) t j , junction temperature ( c) soft-start sourcing current ( a) figure 6. reference voltage (v ref ) vs. temperature figure 7. uvlo vs. temperature figure 8. soft-start sourcing current vs. temperature figure 9. i-limit vs. temperature t j , junction temperature ( c) low-side r ds(on) (m ) 282 281 280 279 278 277 276 276 274 -25 0 50 75 100 125 25 v in = 4.5 v v in = 12 v 11 -25 0 50 75 100 125 25 10 9 8 7 6 5 4 v in = 12 v v in = 4.5 v 801 800.5 800 799.5 799 798.5 798 797.5 v in = 12 v v in = 4.5 v rising falling 4.1 -25 0 50 75 100 125 25 4 3.9 3.8 3.7 3.6 3.5 16 -25 0 25 50 75 100 125 15 14 13 12 11 10 10 -25 0 50 75 100 125 25 9.5 9 8.5 8 7.5 7
ncp3102 http://onsemi.com 6 detailed operating description general ncp3102 is a high efficiency integrated wide input voltage 10 a synchronous pwm buck converter designed to operate from a 5 v to 13.2 v supply. the output voltage of the converter can be precisely regulated down to 800 mv 1.0% when the v fb pin is tied to v out . the switching frequency is internally set to 275 khz. a high gain operational transconductance error amplifier (ota) is used for feedback and stabilizing the loop. duty cycle and maximum pulse width limits in steady state dc operation, the duty cycle will stabilize at an operating point defined by the ratio of the input to the output voltage. the ncp3102 can achieve an 80% duty cycle. there is a built in off-time which ensures that the bootstrap supply is charged every cycle. the ncp3102, which is capable of a 100 nsec pulse width (minimum), can allow a 12 v to 0.8 v conversion at 275 khz. the duty cycle limit and the corresponding output voltage are shown below in graphical format in figure 10 and 12. the light gray area represents the safe operating area for the lowest maximum operational duty cycle and the dark grey area represents the absolute maximum duty cycle and corresponding output voltage. figure 10. duty cycle to output voltage output voltage (v) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 duty cycle 0.8 2.8 4.8 6.8 8.8 10.8 minimum 4.5 v 13.2 v max-maximum min-maximum input voltage range (v cc and bst) the input voltage range for both v cc and bst is 4.5 v to 13.2 v with reference to gnd and phs, respectively. although bst is rated at 13.2 v with reference to phs, it can also tolerate 25 v with respect to gnd. figure 11. maximum input to output voltage input voltage (v) output voltage (v) 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 10 9 8 7 6 5 4 3 d max = 0.7 d max = 0.8 external enable/disable when the comp pin voltage falls or is pulled externally below the 400 mv threshold as shown in figure 12, it disables the pwm logic and the gate drive outputs. in this disabled mode, the operational transconductance amplifier's (eota) output source current is reduced and limited to the soft-start mode of 10 a. always start normal operation condition after disable mode begins by soft-start sequence. this is mentioned in the next section. figure 12. disable circuit - + 16 17 comp/dis v ref 0.8 v fb normal shutdown behavior normal shutdown occurs when the ic stops switching because the input supply reaches uvlo threshold. in this case, switching stops, the internal soft-start, ss, is discharged, and all gate pins go low. the switch node enters a high impedance state and the output capacitors
ncp3102 http://onsemi.com 7 discharge through the load with no ringing on the output voltage. external soft-start the ncp3102 features an external soft-start function, which reduces inrush current and overshoot of the output voltage. soft-start is achieved by using the internal current source of charges the external integrator capacitor of the transconductance amplifier. figure 13 is a typical soft-start sequence. this sequence begins once v cc surpasses its uvlo threshold. during soft-start, as the comp pin rises through 400 mv, the pwm logic and gate drives are enabled. when the feedback voltage crosses 800 mv, the eota will be given control to switch to its higher regulation mode output current of 120 a. in the event of an over current during the soft-start, the overcurrent logic will override the soft-start sequence and will shut down the pwm logic and both the high side and low side gates of the switching mosfets. if the voltage on the comp pin reaches the value of 1.1 v, the device will start switching mosfets. the voltage on the comp pin is proportional to duty cycle in case of the device working in regulated mode. 0.4 v 1.1 v 0.4 v v comp enable v fb 10 a 10 a 120 a isource/ sink ss -10 a startup normal figure 13. soft-start implementation uvlo undervoltage lockout (uvlo) is provided to ensure that unexpected behavior does not occur when v cc is too low to support the internal rails and power the converter. for the ncp3102, the uvlo is set to ensure that the ic will startup when v cc reaches 4.0 v and shutdown when v cc drops below 3.6 v. this permits smooth operation from a varying 5.0 v input source. current limit protection in case of a short circuit or overload, the low side ls-fet will conduct large currents. the controller will shut down the regulator in this situation for protection against overcurrent. the low side r ds(on) sense is implemented by comparing the voltage at the phase node when bg starts going low to an internally generated fixed voltage. if the phase voltage is lower than oc trip voltage, an overcurrent condition occurs and a counter is initiated. when the counter completes, the pwm logic and both hs-fet and ls-fet are turned off. the converter will reinitialize through the soft-start cycle to determine if the short circuit or overload condition has been removed. the minimum turn-on time of the ls-fet is set to 500 ns. the trip thresholds have a -95 mv, +45 mv process and temperature variation when set to -375 mv. the operation of key nodes is displayed in figure 14 for both normal operation and during over current conditions. figure 14. switching and current limit timing ls gate drive bo comparator hs gate drive switch node comparator switch node scp trip voltage scp comparated latch output 2 v 2 v c phase overcurrent protection setting ncp3102 allows the setting of overcurrent threshold ranging from 50 mv to 550 mv, simply by adding a resistor (rocset) bet ween bg and gnd. during a short period of time following v cc rising over uvlo threshold, an internal 10 a current (iocset) is sourced from bg pin, determining a voltage drop across rocset. this voltage drop will be sampled and internally held by the device as overcurrent threshold. the oc setting procedure overall time length is approximately 6 ms. when a rocset resistor is connected between bg and gnd, the programmed threshold is set with an rset values range from 5 k to 55 k . iocth iocset * rocset r ds(on) (eq. 1) in case rocset is not connected, the device switches the ocp threshold to a fixed 375 mv value: an internal safety clamp on bg is triggered as soon as bg voltage reaches 700 mv, enabling the 375 mv fixed threshold and ending oc setting phase. in case of the ocp activation, it is necessary to turn off input supply and start new soft-start sequence. even though the disable function initiates soft-start sequencing, it is impossible to reset the activated ocp by using this disable function. drivers the ncp3102 drives the internal high and low side switching mosfets with 1 a gate drivers. the gate drivers also include adaptive nonoverlap circuitry. the nonoverlap circuitry increase efficiency, which minimizes power dissipation, by minimizing the body diode conduction time. a detailed block diagram of the nonoverlap and gate drive circuitry used in the chip is shown in figure 15.
ncp3102 http://onsemi.com 8 uvlo fault + - 2 v + - 2 v phase tg bst v cc bg gnd uvlo fault pwm out figure 15. block diagram careful selection and layout of external components is required, to realize the full benefit of the onboard drivers. the capacitors between v cc and gnd and between bst and phase must be placed as close as possible to the device. a ground plane should be placed on the closest layer for return currents to gnd in order to reduce loop area and inductance in the gate drive circuit. application section input capacitor selection the input capacitor has to sustain the ripple current produced during the on time of the upper mosfet, so it must have a low esr to minimize the losses. the rms value of this ripple is: iin rms i out d ( 1 d ) (eq. 2) where d is the duty cycle, iin rms is the input rms current, and i out is the load current. the equation reaches its maximum value with d = 0.5. losses in the i nput capacitors can be calculated with the following equation: p cin esr cin iin rms 2 (eq. 3) where p cin is the power loss in the input capacitors and esr cin is the effective series resistance of the input capacitance. due to lar ge di/dt through the input capacitors, electrolytic or ceramics should be used. if a tantalum capacitor has to be used, surge protection is needed. otherwise, capacitor failure could occur. calculating input startup current to calculate the input startup current, the following equation can be used: i inrush c out v out t ss (eq. 4) where i inrush is the input current during startup, c out is the total output capacitance, v out is the des ired out put voltage, and t ss is the soft-start interval. if the inrush current is higher than the steady state input current during maximum load, then the input fuse should be rated accordingly, if one is used. calculating soft-start time to calculate the soft-start time, the following equation can be used. t ss c p c c * v i ss (eq. 5) where c c is the compensation as well as the soft-start capacitor. c p is the additional capacitor that forms the second pole. i ss is the soft-start current v is the comp voltage from zero to until it reaches regulation. v comp v out 1.1 v v figure 16. soft-start the above calculation includes the delay from comp rising to when output voltage becomes valid. to calculate the time of output voltage rising to when it reaches regulation; v is the difference between the comp voltage reaching regulation and 1.1 v. output capacitor selection selection of the right value of input and output capacitors determines the behavior of the buck converter. in most high power density applications the capacitor size is most important. ceramic capacitor is necessary to reduce the high frequency ripple voltage at the input of converter. this capacitor should be located near the device as possible. added electrolytic capacitor improved response of relative slow load change. the required output capacitor will be determined by planned transient deviation requirements. usually a combination of two types of capacitors is recommended to meet the requirements. first, a ceramic output capacitor is needed for bypassing high frequency noise. second, an electrolytic output capacitor is needed to achieve good transient response. in fact, during load transient, for the first few microseconds the bulk capacitance supplies current to the load. the controller immediately recognizes the load
ncp3102 http://onsemi.com 9 transient and sets the duty cycle to maximum, but the current slope is limited by the inductor value. during a load step transient the output voltage initially drops due to the current variation inside the capacitor and the esr. (neglecting the effect of the ef fective series inductance (esl)): v out-esr i out esr cout (eq. 6) where v out-esr is the voltage deviation of v out due to the effects of esr and the esr cout is the total effective series resistance of the output capacitors. table 1. shows values of voltage drop and recovery time of the ncp3102 demo board with the configuration shown in figure 20. the transient response was measured for the load current step from 5 a to 10 a (50% to 100% load). input capacitors are 2x47 f ceramic and 2x270 f os-con, output capacitors are 2x100 f ceramic and os-con as mentioned in table 1. typical transient response waveforms are shown in figure 17. more information about os-con capacitors is available at http://www.edc.sanyo.com. table 1. transient response versus output capacitance (50% to 100% load step) c out ( f) os-con drop (mv) recovery time ( s) 100 226 504 150 182 424 220 170 264 270 149 233 560 112 180 680 100 180 820 96 180 1000 71 180 2x680 60 284 2x820 48 224 figure 17. typical waveform of transient response a minimum capacitor value is required to sustain the current during the load transient without discharging it. the voltage drop due to the output capacitor discharge is given by the following equation: v out-discharge i out 2 l out 2 c out v in d v out (eq. 7) where v out-discharge is the voltage deviation of v out due to the effects of discharge, l out is the output inductor value and v in is the input voltage. inductor selection both mechanical and electrical considerations influence the selection of an output inductor. from a mechanical perspective, smaller inductor values generally correspond to smaller physical size. since the inductor is often one of the largest components in the regulation system, a minimum inductor value is particularly important in space-constrained applications. from an electrical perspective, the maximum current slew rate through the output inductor for a buck regulator is given by: slewrate lout v in v out l out (eq. 8) this equation implies that larger inductor values limit the regulator's ability to slew current through the output inductor in response to output load transients. consequently, output capacitors must supply the load current until the inductor current reaches the output load current level. this results in larger values of output capacitance to maintain tight output voltage regulation. in contrast, smaller values of inductance increase the regulator's maximum achievable slew rate and decrease the necessary capacitance, at the expense of higher ripple current. the peak-to-peak ripple current is given by the following equation: ipk-pk lout v out ( 1 d ) l out 275khz (eq. 9) where i pk-pk lout is the peak to peak current of the output. from this equation it is clear that the ripple current increases as l out decreases, emphasizing the trade-off between dynamic response and ripple current. in order to achieve high efficiency, coils with a low value of direct current resistance (dcr) have to be used. for example: coilcraft mlc1555-302ml and ser2013-362ml). feedback and compensation the output voltage is adjustable from 0.8 v to 5 v as shown in table 2. the adjustment method requires an external resistor divider with its center tap tied to the fb pin. it is recommended to have a resistance between 1.5 k and 5 k . the selection of low value resistors reduces efficiency, alternatively high value resistance of r2 causes decrease in output voltage accuracy due to the bias current in the error amplifier. the output voltage error of this bias current can be estimated by using the following equation:
ncp3102 http://onsemi.com 10 error(%) r2 * i bias v ref * 100 (eq. 10) error = r2 * 1.25 * 10 -5 (%) once r2 is calculated above r3 can be calculated to select the desired output voltage as shown in the following equation: r3 v ref v out v ref *r2 (eq. 11) table 2 shows r3 values for frequently used output voltages. fault figure 18. fb circuit - + - + 13 vcc 16 17 fb comp dis por uvlo 0.8v v ref r2 r3 c soft-start c comp r comp v out table 2. output voltages and divider resistors v out (v) r2 (k ) r3 (k ) e24 r3 (k ) calculated 0.8 1.8 none none 1.0 0.51 2.0 2.040 1.2 0.75 1.5 1.500 1.5 1.3 1.5 1.486 1.8 1.6 1.3 1.280 2.5 1.6 0.75 0.753 3.3 1.6 0.51 0.512 5.0 2.7 0.51 0.514 figure 18 shows a typical type ii operational transconductance error amplifier (ot a). the compensation network consists of the internal error amplifier and the impedance networks zin (r3) and external zfb (r comp , c comp and c soft-start ). the compensation network has to provide a closed loop transfer function with the highest 0 db crossing frequency to have fast response (but always lower than f sw /8) and the highest gain in dc conditions to minimize the load regulation. a stable control loop has a gain crossing w ith -20 db/decade sl ope and a phase margin greater than 45 . include worst-case component variations when d etermining phase margin. loop stability is defined by the compensation network around the ota, the output capacitor, output inductor and the output divider. figure 19 shows the open loop and closed loop gain plots. it is possible to use compensation calculator software tool from on semiconductor website. this tool can be downloaded from http://www.onsemi.com. figure 19. gain plot for the error amplifier gain (db) frequency (hz) 100 1000 10 k 100 k 1000 k open loop, unloaded gain closed loop, unloaded gain error amplifier compensation network a gain = gmr 1 b f z f p thermal considerations the package thermal resistance can be obtained from the specifications section of this data sheet and a calculation can be made to determine the ncp3102 junction temperature. however, it should be noted that the physical layout of the board, the proximity of other heat sources such as mosfets and inductors, and the amount of metal connected to the ncp3102, impact the temperature of the device. the pcb is used also as the heatsink. double or multi layer pcbs with thermal vias between places with the same electrical potential increase cooling area. a 70 m thick copper plating is a good solution to eliminate the need for an external heatsink. layout considerations when designing a high frequency switching converter, layout is very important. using a good layout can solve many problems associated with these types of power supplies as transient occur. external compensation components (r1, c9) are needed for converter stability. they should be placed close to the ncp3102. the feedback trace is recommended to be kept as far from the inductor and noisy power traces as possible. the resistor divider and feedback acceleration circuit (r2, r3, r6, c13) is recommended to be placed near to input fb (pin 16, ncp3102). switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. these interconnecting impedances should be minimized by using wide, short printed circuit traces. the critical components should be located together as close as possible using ground plane construction or single point grounding. the inductor and output capacitors should be located together as close as possible to the ncp3102.
ncp3102 http://onsemi.com 11 figure 20. schematic diagram of ncp3102 evaluation board 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 19 20 18 17 16 14 15 13 12 11 32 31 33 34 35 37 36 38 39 40 pwrphs pwrgnd pwrgnd pwrgnd tgin bst agnd cphs tgout pwrvcc bg vcc agnd agnd fb comp nc agnd pwrphs pwrvcc rboost 3r3 c12 220n cboost 2n2 r7 or 732 r1 c9 33n c10 120 c11 220n c2 c4 c15 + 47 47 in in r5 2r2 d3 d2 2xmbrs140t3 rsn 10r r6 ocpset l1 3.3 h csn 470 1 2 3 phase d1 bat54t1 r2 1.6k r3 510 r8 200 c13 22n r4 20r 1 2 3 1 2 3 1 2 3 1 2 3 x1 out out c16 100 c8 100 c5 ncp3102 + 1m rlo6 rlo5 rlo4 rlo3 rlo2 rlo1 rlo7 rlo8 rlo9 clo1 clo2 clo3 rlo10 + q1 q2 q3 270 +
ncp3102 http://onsemi.com 12 schematic diagram of the ncp3102 demoboard is shown in figure 20 and the actual pcb layout is shown in figure 21. the corresponding bill of material is summarized in table 3. parameters of the board were tested with input voltage v in = 5 v to 13.2 v and with various output loads between 0 a and 10 a. the board includes a few components used for transient measurements. the load current range can be selected by switches 1 to 3 to give a range of 0 a - 10 a with 2.5 a steps. a square wave signal with a 10% duty cycle and a 10 v amplitude has to be connected to the x1 connector to enable the load testing.
ncp3102 http://onsemi.com 13 table 3. bill of material position value description part no: footprint quantity manufacturer r1 732 resist. smd rmc1/8w 1206 1% 732r 1206 1 multicomp r2 1.6k resist. smd rmc1/8w 1206 1% 1k6 1206 1 multicomp r3 510 resist. smd rmc1/8w 1206 1% 510r 1206 1 multicomp rboost 3.3 resist. smd 232273463308 1206 1 phycomp r5 2.2 resist. smd 232272462208 1206 1 phycomp r6 ocp set. resist. smd 1206 1 r7 0 resist. smd tl2br010fte 1206 1 tyco elect. r8 200 resist. smd wcr 1206 200r 2%. 1206 1 welwyn rsn 10 resist. smd 232271161109 1206 1 phycomp r4* 20 resist. smd rca120620r0fkea 1206 1 vishay rlo1* 1.0 resistor 1w mcf 1w 1r special 1 multicomp rlo2* 1.8 resistor 1w mcf 1w 1r8 special 1 multicomp rlo3* 2.2 resistor 1w mcf 1w 2r2 special 1 multicomp rlo4* 3.3 resistor 1w mcf 1w 3r3 special 1 multicomp rlo5* 2.2. resistor 1w mcf 1w 2r2 special 1 multicomp rlo6* 3.3 resistor 1w mcf 1w 3r3 special 1 multicomp rlo7* 1k resist. smd 232272461002 1206 1 phycomp rlo8* 1k resist. smd 232272461002 1206 1 phycomp rlo9* 1k resist. smd 232272461002 1206 1 phycomp rlo10* 75 resist. smd rmc1/8w 1206 1% 75r 1206 1 multicomp c2, c4 47 f capac. ceram c1210c476m9pac7800 1210 2 kemet c15 0.27mf cap.os-con 16sp270m special 1 sanyo c16 1mf cap.os-con 4sp1000m special 1 sanyo c5, c8 100 f capac. ceram cs1210c107m9pac7800 1210 2 kemet cboost 2.2nf capac. ceram 12067c222kat2a 1206 1 avx c11, c12 220nf capac. ceram 12065g224zat2a 1206 1 avx c9 33nf capac. ceram b37972k5333k-mr 1206 1 tycho elect. c10 120pf capac. ceram 2250 001 11537 1206 1 phycomp c13 22nf capac. ceram 2238 581 15641 1206 1 phycomp csn 470pf capac. ceram 12067a471jat1a 1206 1 avx clo1-3* 470pf capac. ceram 12067a471jat1a 1206 1 avx d1 bat54t1 diode bat54t1g sod123 1 on semiconducor d2-3 mbrs140t3 diode mbrs140t3g smb 2 on semiconducor l1 3.3 h coil do5010h-332m do5010h 1 coilcraft q1-3* ntd4810 mosfet ntd4810nh dpak 3 on semiconductor ic1 ncp3102 i.c. ncp3102mntxg qfn40 1 on semiconductor *parts marked with * and highlighted in grey are only necessary for transient response and phase-gain feedback measuring.
ncp3102 http://onsemi.com 14 figure 21. pcb layout evaluation board (110mm x 100mm)
ncp3102 http://onsemi.com 15 measured performance of ncp3102 demoboard is shown in figures 22 through 25. figure 22. overcurrent protection r ocp resistance (k ) figure 23. efficiency (v out = 3.3 v) figure 24. transient response (v in = 12 v, v out = 3.3 v, i out = 5 a to 10 a step) output capacitors: 2x mlcc 100 f and 820 f os-con figure 25. feedback frequency response (v in = 12 v, v out = 3.3 v) phase (deg) gain (db) frequency (hz) -40 -30 -20 -10 0 10 20 30 40 50 100 1000 10000 100000 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 phase gain 0 2 4 6 8 10 12 14 16 18 4 t j = 25 c t j = 125 c 5 6 7 8 9 10 11 12 13 t j = 70 c i ocp (a) 60 65 70 75 80 85 90 95 100 012345678910 output current (a) efficiency (%) 4.5 v 13.2 v 12 v 10 v 8 v 6 v
ncp3102 http://onsemi.com 16 figure 26. temperature conditions (v in = 12 v, v out = 3.3 v, i out = 10 a) steady state, no additional cooling ordering information device package temperature grade shipping ? ncp3102mntxg qfn40 (pb-free) for 0 c to +70 c 2500 / tape & reel NCP3102BMNTXG qfn40 (pb-free) for -40 c to +85 c 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp3102 http://onsemi.com 17 package dimensions qfn40 6x6, 0.5p case 485ak-01 issue a seating 0.15 c (a3) a a1 b 1 11 21 40 2x 2x g3 40x 10 30 l 40x bottom view top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 31 e a 0.10 b c 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from terminal 4. coplanarity applies to the exposed pad as well as the terminals. dim min max millimeters a 0.80 1.00 a1 --- 0.05 a3 0.20 ref b 0.18 0.30 d 6.00 bsc d2 2.45 2.65 e 6.00 bsc 2.00 e2 1.80 e 0.50 bsc l 0.30 0.50 k 0.20 --- plane dimensions: millimeters 0.50 0.58 0.30 40x 2.31 6.30 soldering footprint 1 d3 3.10 3.30 d4 1.70 1.90 d5 0.85 1.05 1.63 e3 1.43 2.35 e4 2.15 g3 2.30 2.50 g2 2.10 2.30 note 4 e/2 g2 g2 d3 1 11 21 40 10 30 bottom view 31 e2 d5 auxiliary d2 d4 1.01 3.26 40x 1.58 1.96 1.86 2.62 0.72 0.72 note 3 k e3 e4 g3 g2 g3 6.30 pitch 0.92 0.92 0.92 0.72
ncp3102 http://onsemi.com 18 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800-282-9855 toll free ?usa/canada europe, middle east and africa technical support: ?phone: 421 33 790 2910 japan customer focus center ?phone: 81-3-5773-3850 ncp3102/d literature fulfillment : ?literature distribution center for on semiconductor ?p.o. box 5163, denver, colorado 80217 usa ? phone : 303-675-2175 or 800-344-3860 toll free usa/canada ? fax : 303-675-2176 or 800-344-3867 toll free usa/canada ? email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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